Visual Designer Studio

Supported interfaces

Altera Avalon (AXI like)
- Memory mapped
- streaming
ARM AMBA AXI
- AXI3
- AXI4
- AXI4Lite
- AXI4Stream
- AXI4NoC
- AXI5

Conduit
- directly exported, no interaction with connectivity
Clock
- Specify frequency
- AXI and Avalon interfaces have associated clock (used to introduce clock crossing where required)
Reset
- has associated clock
- AXI and Avalon interfaces have associated reset (used to introduce reset synchronisation where required)
Interrupt

Interconnect generation

Memory mapped interconnect
- Any master to any slave
- interface adaptation inferred
  - associated clock and reset
- Option to explicitly insert components recommended
  - clock crossing bridge
  - width adaption
  - burst adaption
- Variable pipelining at system level to trade latency vs frequency
Streaming
- Any master to any slave

Software integration

The columns renders left to right in the reveal.js generated by pandoc

graph TB
    hw[hardware arch defined in vds] --> bsp[bsp generate niosv_bsp]
    bsp --> app[application cmake files niosv_app]
    app --> cmake
    cmake --> bin[elf, hex object files]
    bin --> hw_c[update memory content for mem .ip]
    hw_c --> rbf[FPGA programming file with Nios V program]
    bin --> dbg[debug elf using gdb or riscfree]
    rbf --[mif update]-->rbf2[rbf with preserved layout]
    bin --> rbf2

BSP editor niosv-bsp and application template editor niosv-app available as cmd line applications or GUI for BSP editor.
- Generates cmake based build files
- Optional RiscFree IDE available

Visual Designer Studio

Supported interfaces

Interconnect generation

Software integration

Tour of the tool